OpenVVVF/docs
OPENVVVF
Software Manual

Architecture

STM32H723ZG main MCU software architecture - layers, state machine, FOC, modulation, sensing, and safety mechanisms.

Document IDOV-SW-MAINMCU-ARCH
Version0.1
Date2026-08-08
Statusdraft
Applies toopenvvvf-control-module, software-target-main-mcu
Product lineopenvvvf
Normative referencesOV-SAF-HARA-CORE, OV-CA-SWM-INDEX
Index / Software / Main MCU Software / Architecture / Architecture
OV-SW-MAINMCU-ARCH · v0.1 · draft · 2026-08-08
DoctypeSoftware Manual
Doc idOV-SW-MAINMCU-ARCH
Product lineopenvvvf
Applies toopenvvvf-control-module, software-target-main-mcu
Version0.1
Date2026-08-08
Statusdraft
PlaceholderTrue
DescriptionSTM32H723ZG main MCU software architecture - layers, state machine, FOC, modulation, sensing, and safety mechanisms.
Nav order411
Normative refsOV-SAF-HARA-CORE, OV-CA-SWM-INDEX
Placeholder / Under Revision - This page is incomplete or out of date and will be revised.

Architecture

Placeholder - This document will define the main MCU software architecture from scratch. The old SWAD is being abandoned.

Planned sections

  1. Design principles and layer model
  2. System state machine
  3. FOC and modulation library
  4. Multi-rate ADC and current sensing
  5. CAN communication and protocol model
  6. Safe-state and fault management
  7. Input validation and parameter storage
  8. Power-loss estimator and thermal model
  9. Memory layout and startup
  10. Traceability to HARA FSRs